 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| Electronic Design Department Data Sheet Poland, 44-100 Gliwice, Dubois 16 Phone/Fax: +48 32 2311171, 2313027 ipcenter@evatronix.pl www.evatronix.pl January 8, 2008 R8051XC Configurable Microcontroller Overview The R8051XC is a fast, configurable, single-chip 8-bit microcontroller core that can implement a variety of fast processor variations executing the MCS(R) 51 instruction set. The efficient core design runs an average of 8.1 times faster than the 80C51. A rich set of optional features and peripherals enable designers to closely match the core with their specific application and hardware requirements (FPGA, ASIC, or structured ASIC). These options include memory pointers, interrupts, interfaces for serial communication, I2C and SPI interfaces, a timer system, I/O ports, power management unit, multiplication-division unit, watchdog timer, DMA controller and real-time clock. Integrated on-chip debugging using either the native OCDS or FS2's OCI is also available. The R8051XC is an extension of our proven 8051 family of processor cores, which have been successfully implemented in a hundred different customer products. Designers can purchase a custom configuration by selecting a set of options that best meets their needs, or choose from these three prepackaged versions of the core: R8051XC-F is the fully-configurable version of the core, with all options included. R8051XC-A matches our earlier R8051, with a set of peripherals making it compatible with the Intel 80C31 (see details in the Configurations section). R8051XC-B matches our earlier R80515 core, with a set of peripherals making it compatible with the Siemens 80C515 and 80C517. Representative ASIC implementation results for the different configurations range from under 9,000 gates for the R8051XC-A to under 55,000 for all available options (except debug). Speed ranges from 250 to 350 MHz and above, depending on the technology. Developed for easy reuse in ASIC and FPGA implementations, the core is strictly synchronous, with positive-edge clocking, no internal tri-states, and a synchronous reset. Optional Features and Peripherals External Memory Interface Addresses up to 8 MB of Program Memory (when using memory banking) Addresses up to 8 MB of Data Memory (when using memory banking) One, two, or eight Data Pointers for fast data block transfer Additional Arithmetic Unit supporting Data Pointers auto-increment/-decrement and auto-switch Supports external DMA controller through HOLD interface Program memory write mode Multiplication-Division Unit 16 x 16-bit multiplication 32/16- and 16/16-bit division 32-bit normalization and L/R shifting Special Function Registers interface Services from 40 to 118 External Special Function Registers (depending on peripheral configuration) Interrupt Controller: four priority levels with eighteen interrupt sources, or two priority levels with six sources Power Management Unit with power-down modes (IDLE and STOP) Interface for on-chip debug: native On-Chip Debug Support (OCDS Direct Memory Access (DMA) Controller Up to eight independent channels Read/Write Access to all memory spaces (incl. SFR) Linear addressing (up to 8MB) Address auto-increment/decrement Synchronous/asynchronous Mode Software Trigger/Hardware Trigger 16-bit Timers/Counters: 80C51-like Timers 0 and 1 80C515-like Timer 2; it includes a Compare/Capture Unit with four 16-bit Compare registers for Pulse Width Modulation; four external Capture inputs for Pulse Width Measuring; and a 16-bit Reload register for Pulse Generation Input/Output ports Up to four 8-bit I/O ports; alternate port functions, such as external interrupts and the serial interface are separated, providing extra port pins when compared with the standard 8051 Serial 0: a full-duplex serial interface (80C51-like), equipped with additional baud rate generator Serial 1: an asynchronous-only version of Serial 0 15-bit programmable Watchdog timer SPI Master/Slave interface One or two I2CTM Master/Slave interfaces Features Eight-bit instruction decoder for MCS(R) 51 instruction set Executes instructions with one clock per cycle (versus twelve for standard 80C51) for an average 8.1 times speed increase ALU performs 8-bit arithmetic and logical operations and Boolean manipulations; 8-bit multiplication and division can be optionally removed to save silicon Flexible external memory interface can address up to 8MB of Program Memory and 8MB of Data Memory Space (when the extended memory option is included) Can address up to 256 B of Internal Data Memory SFR interface services 40 to 118 external Special Function Registers (depending on configuration) Extensive core configurability: choose options as needed, or get fully-configurable version Copyright (c) 2005 - 2008 Evatronix SA R8051XC-DSN-1HV28F26S00-200 Page 1 of 8 R8051XC Configurable Microcontroller Configurable Microcontroller Implementation Results R8051XC reference designs have been evaluated in a variety of technologies. The following table presents sample results for the R8051XC-A configuration. Device UMC 0.25 um UMC 0.18 um Area 13k gates 13.3k gates Speed 155 MHz 210 MHz Performance The R8051XC is designed to run at frequencies up 230 MHz on typical 0.18-micron process. It uses from 6K to 70K gates depending on the technology and configuration. The R8051XC is a technology independent design that can be implemented in a variety of process technologies. The architecture eliminates redundant bus states and implements parallel processing of fetch and execution phases. Since a cycle is aligned with memory fetch when possible, most of the 1-byte instructions are performed in a single cycle. The R8051XC uses 1 clock per cycle. This leads, together with other extensions (mutli-DPTR, MDU) to performance improvement at rate of 9.6 (in terms of DMIPS) with respect to the Intel device working with the same clock frequency. The table below shows the speed advantage of the R8051XC over the standard 8051. A speed advantage of 12 means that the R8051XC performs the same instruction twelve times as fast as the 8051. Speed advantage 24 12 9.6 8 6 4 Average: 8.1 Number of instructions 1 31 2 21 41 15 Sum: 111 Number of opcodes 1 101 2 38 94 19 Sum: 255 Notes: R8051XC-A Configuration optimized for speed Configurability A spreadsheet-like Design Configurator is available to help in the selection of the core's many options. The configurable options include: Size of external data/program memory: 64 KB to 8 MB Number of DPTR registers: 1, 2 or 8 Arithmetic support for DPTRs: yes or no Two types of interrupt controller: Type 51 Type 515 interrupt sources: 0...6 0 ... 18 external interrupts: 0...2 0 ... 13 priority levels: 2 4 Number of 8-bit I/O ports: 0 to 4 Number of 16-bit timers: 0 to 3 Number or serial ports: 0, 1, or 2 Watchdog timer: yes or no Multiplication-Division unit: yes or no DMA Channels: 0 to 8 I2C master-slave interface: 0, 1, or 2 SPI master-slave interface: yes or no On-chip debug support: OCDS, FS2 OCI, or none For OCDS: Number of hardware breakpoints: 2 to 8 Program trace: yes or no Data & program trace: yes or no Rarely used instructions MUL, DIV, DA: yes or no Software Reset: yes or no Support for external DMA operations: yes or no Real Time Clock: yes or no The 8051-like prepackaged R051XC-A core includes: 64kB memory interface, two timers, one serial port, four parallel I/O Ports, two-level interrupt controller, and two DPTR registers. The 80515-like prepackaged R8051XC-B core includes: 64kB memory interface, three timers, two serial ports, four parallel I/O ports, watchdog timer, multiplication-division unit, and two DPTR registers. ASIC The average of speed advantage is 8.1. However, the real speed improvement seen in any system will depend on the instruction mix. Performance Configuration: Dhrystones/Mhz Basic 113.9 Multiple DPTR 142.2 Multiple DPTR+auto-inc 154.1 MDU+Multiple DPTR+auto-inc 157.8 Ratio 6.9 8.6 9.3 9.6 The following table shows example implementation results for 0.18 um technology for range of predefined configurations. Configuration R8051XC CPU. R8051XC-A R8051XC-B R8051XC-F Speed1 230 MHz 210 MHz 210 MHz 200 MHz Area 2 6.2k gates 11.2k gates 17k gates 55.1k gates Notes: 1 2 Implemented with optimization set for speed Implemented with constraints set for minimal area Copyright (c) 2005 - 2008 Evatronix SA R8051XC-DSN-1HV28F26S00-200 Page 2 of 8 R8051XC Configurable Microcontroller Configurable Microcontroller Block Diagram External Memory Interface On Chip Memory/SFR Interface OCI Interface R8051XC CPU DMA OCDS OCDS Interface TimerO inputs Timer1 inputs External Interrupt inputs TIMERO TIMER2 4 x CCUPORT Timer2 inputs TIMER1 WATCHDOG EXTINT ISR MDU 515-like 51-like Watchdog input SERIAL0 I2C Interface Secondary I2C Interface SPI Interface I2C SERIAL1 SEC I2C PORTS SPI MS Serial0 interfaces Serial1 interfaces port0 port1 port2 port3 SYNCNEG PMURSTCTRL WAKEUPCTRL RTC engine clock peripheral clock Hardware reset PMURSTCTRL WAKEUPCTRL Engine clock output Peripheral clock output RCT Clock & Reset One of two possible components Constant elements clock clock_sync Optional elements Copyright (c) 2005 - 2008 Evatronix SA R8051XC-DSN-1HV28F26S00-200 Page 3 of 8 R8051XC Configurable Microcontroller Configurable Microcontroller Functional Description The core is partitioned into modules as shown in the block diagram and described below. Pin Description Name Type Polarity/ Bus size General signals clkcpu I Rise Engine clock Pulse for internal circuits, which are stopped in IDLE or STOP mode Engine clock enable output External control for the "clkcpu" clock, when set to 1 the "clkcpu" input should be running, otherwise the "clkcpu" should be stopped Peripheral clock Pulse for internal circuits, which are stopped in STOP mode Peripheral clock enable output External control for the "clkper" clock, when set to 1 the "clkper" input should be running, otherwise the "clkper" should be stopped Hardware reset input High level on this pin for two clock cycles while the oscillator is running resets the device Reset output Set active when either the Hardware Reset, Watchdog Timer, Software Reset or OCDS generates reset signal to the core Start Watchdog Timer input High level on this pin during reset starts the watchdog timer immediately after reset is released Description Central Processing Unit The CPU fetches instructions from program memory and uses RAM or SFRs as operands. Provides the ALU for 8-bit arithmetic, logic, multiplication and division operations, and Boolean manipulations. The RAM and SFR interface can address up to 256 bytes of Read/Write Data Memory Space and built-in and off-core Special Function Registers. The memory interface can address from 64KB to 8MB of Program Memory, and from 64KB up to 8MB of External Data Memory. It uses a HOLD interface to support any external DMA controller, and it eases the connection to memories using a demultiplexed address/data bus. The variable-length code fetch and MOVC to access fast or slow program memory, and similarly a variable-length MOVX to access fast or slow RAM or peripherals are provided. clkcpuen O High clkper I Rise clkperen O High DMA Controller The Direct Memory Access (DMA) Controller contains up to eight individual Channels, each capable of transferring data from or to any addressable location (program memory, internal or external data memory, or SFR). Each channel can work in synchronous mode (when just one byte is transferred at each trigger) or asynchronous mode (when all the data is transferred at each trigger). Transfers can be triggered by software or by specified interrupt source. reset I High ro O High Ports The parallel I/O port controller serves up to four parallel 8-bit I/O ports to be used with off-core buffers. It is compatible with the classic 80C51, but lacks the multiplexed memory bus feature and alternate functions. (These could be combined offcore if required). swd I High Timers 0 and 1 Timers 0 and 1 are nearly identical, and they each have these three modes: 13-bit timer/counter, 16-bit timer/counter, and 8-bit timer/counter with auto reload. Timer 0 has an additional mode: two 8-bit timers. Each timer can also count external pulses (1 to 0 transition) on the corresponding t0 or t1 pin. Another option is to gate the timer/counter using an external control signal, which allows it to measure the pulse width of external signals. rtcx rtcreset I I Real Time Clock signals Rise/Fall High RTC 32,768kHz clock input RTC reset input Port 0 port0i port0o I O 8 8 8-bit bi-directional I/O port with separated inputs and outputs Port 1 port1i port1o I O 8 8 8-bit bi-directional I/O port with separated inputs and outputs Timer 2 Operates as a timer, event counter, or gated timer. In timer mode, the Timer 2 can be incremented every 12 or 24 clock cycles, depending on the prescaler setting. In event counter mode, Timer 2 is incremented when an external signal changes from 1 to 0 (sampled every machine cycle). Timer 2 is incremented in the cycle following the one in which that transition was detected. In gated timer mode, Timer 2's incrementing is gated by an external signal. A Timer 2 reload can be executed in two modes. In Mode 0, the reload signal is generated by a Timer 2 overflow (auto reload), while in Mode 1 it is generated by a negative transition at the corresponding input pin t2ex. Port 2 port2i port2o I O 8 8 8-bit bi-directional I/O port with separated inputs and outputs Port 3 port3i port3o I O 8 8 8-bit bi-directional I/O port with separated inputs and outputs Copyright (c) 2005 - 2008 Evatronix SA R8051XC-DSN-1HV28F26S00-200 Page 4 of 8 R8051XC Configurable Microcontroller Configurable Microcontroller Compare-Capture Unit The CCU within Timer2 performs Compare and Capture functions. For the Compare function, values stored in four 16bit compare/capture registers are compared with the contents of the Timer 2 register. The results are signaled on the "ccubus" outputs and interrupts are generated. For the Capture function actual timer/counter contents can be saved into one of four 16-bit registers upon an external event (Mode 0) or software write operation (Mode 1). Pin Description - Continued Name Type Polarity/ Bus size Low/Fall Low/Fall Fall/Rise Fall/Rise Rise Rise Rise Rise Rise Rise Rise Rise Rise Description External interrupt inputs int0 int1 int2 int3 int4 int5 int6 int7 int8 int9 int10 int11 int12 I I I I I I I I I I I I I External interrupt 0 External interrupt 1 External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 External interrupt 7 External interrupt 8 External interrupt 9 External interrupt 10 External interrupt 11 External interrupt 12 Multiplication Division Unit This on-chip arithmetic unit performs these unsigned integer operations: 16 x 16 bit multiplication 32 / 16 bit division and 16 / 16 bit division 32 bit normalization and L/R shifting The MDU allows operations to occur concurrently to and independent of the engine activity. Serial 0 and 1 The core includes two fully independent serial ports for simultaneous communication over two channels. They can operate in identical or different modes and at different communication speeds. Serial Port 0 is capable of both synchronous and asynchronous transmission while Serial 1 provides asynchronous mode only. In synchronous mode, the microcontroller generates a clock and operates in half-duplex mode. In asynchronous mode, full duplex operation is available. Received data is buffered in a holding register, which allows the serial ports to receive an incoming word before the software has read the previous value. Serial Port 0 offers the following communication protocols: Synchronous mode, fixed baud rate 8-bit UART mode, variable baud rate 9-bit UART mode, variable or fixed baud rate Serial Port 1 has two operating modes: 8-and 9-bit UART mode, variable baud rate Both include an additional Baud Rate Generator. Serial 0 interface rxd0i rxd0o txd0 I O O Serial 0 receive data Serial 0 transmit data Serial 0 transmit data or receive clock in mode 0 Serial 1 interface rxd1 txd1 I O Serial 1 receive data Serial 1 transmit data Timers inputs t0 t1 t2 t2ex I I I I Fall Fall Fall Fall Timer 0 external input Timer 1 external input Timer 2 external input Timer 2 capture trigger Compare - Capture Unit cc(0) I I O Rise/Fall Rise 4 Compare/Capture 0 input Compare/Capture 1-3 inputs Compare/Capture outputs cc(3:1) ccubus Power Management Unit & Reset Control Generates clock enable signals for the main CPU and for peripherals; serves Power Down Modes IDLE and STOP; and generates an internal synchronous reset signal (upon external reset, watchdog timer overflow or software reset condition). The IDLE mode leaves the clock of the internal peripherals running. Power consumption drops because the CPU is not active. Any interrupt or reset will wake the CPU. The STOP mode turns off all internal clocks. The CPU will exit this state with an external interrupt or reset. Internally generated interrupts (timer, serial port, watchdog, ...) are disabled since they require clock activity. External memory interface mempsack memack memdatai memdatao memaddr mempswr mempsrd memwr memrd I I I O O O O O O High High 8 8 16..23 High High High High Program memory read acknowledge Data memory acknowledge Memory data input Memory data output Memory address Program store write enable Program store read enable Data Memory write enable Data Memory read enable Wake-up Control The Wake-up From Power-Down Mode Control Unit services two external interrupts during power-down modes. They can combinationally force the clock enable outputs back to active state so the clock generation can be resumed. Internal Data Memory interface ramdatai ramdatao ramaddr ramwe ramoe I O O O O 8 8 8 High High Data bus input Data bus output Data file address Data file write enable Data file output enable Copyright (c) 2005 - 2008 Evatronix SA R8051XC-DSN-1HV28F26S00-200 Page 5 of 8 R8051XC Configurable Microcontroller Configurable Microcontroller Real Time Clock The RTC provides a real-time count with a resolution of 1/256th second and range of 179 years. It can set and read seconds, minutes, hours, day of the week, and the date, represented by a 16-bit number interpreted by software. An alarm function can generate interrupts periodically or at a specific time, and these may be used to wake up from IDLE/STOP mode. Pin Description - Continued Name Type Polarity/ Bus size 8 8 7 High High Description External Special Function Registers interface sfrdatai sfrdatao sfraddr sfrwe sfroe I O O O O SFR data bus input SFR data bus output SFR address SFR write enable SFR output enable SFR Mux The SFR Multiplexer provides a common bus multiplexer for all the internal and external Special Function Registers. OCDS The OCDS unit serves interface for On-Chip Debug Support through an IEEE1149.1 (JTAG) port. The OCDS unit provides the following functions: Run, Stop, Single-step Software breakpoint Debugger program execution Hardware breakpoints Read/Write Access to Program Memory, External/Internal Data Memory and SFRs Program Trace and Data Trace (optional) External memory interface for rising-edge triggered synchronous memories memdatao_comb memaddr_comb mempswr_comb mempsrd_comb memwr_comb memrd_comb O O O O O O 8 16..23 High High High High Memory data output Memory address Program store write enable Program store read enable Data Memory write enable Data Memory read enable Watchdog Timer A 15-bit counter that is incremented every 24 or 384 clock cycles. After an external reset, it is disabled and all registers are set to zeros. It can be started by applying an active input during reset (hardware automatic start) or by setting the enable bit by software. Once started, it cannot be stopped unless the external reset signal becomes active. When the Watchdog enters the state of 7CFFh, it activates a dedicated flag and forces internal reset. It can be avoided by refreshing the Watchdog with software before it reaches 7CFFh. Internal Data Memory interface for rising-edge triggered synchronous memories ramdatao_comb ramaddr_comb ramwe_comb ramoe_comb O O O O 8 8 High High Data bus output Data file address Data file write enable Data file output enable External Special Function Registers interface for rising-edge triggered synchronous devices sfrdatao sfraddr sfrwe sfroe O O O O 8 7 High High SFR data bus output SFR address SFR write enable SFR output enable Interrupt Service Routine Unit The R8051XC provides two types of interrupt controllers: an 8051-compatible with up to six interrupt sources and two priority levels, or an 80515-compatible with up to eighteen interrupt sources and four priority levels. Each source has its own request flag(s) located in a dedicated SFR. Each interrupt requested by the corresponding flag can be individually enabled or disabled by dedicated enable bits in the SFRs. On-Chip Instrumentation interface (OCI)* debugreq debugstep debugprog debugack flush fetch waitstaten acc I I I O O O O O High High High High High High Low 8 Debug mode request Debug mode single-step Debugger program select Debugger acknowledge signal First fetch after branch indicator Fetch from program memory, when flush inactive Waitstate indicator Accumulator register output Primary and Secondary I2CTM Interfaces The primary (I2C) and secondary (SEC_I2C) I2C Bus Controllers each provide a serial interface that meets the Philips I2C bus specification v1.0 and support all master/slave receiver/transmitter modes. Each is a true multi-master bus controller, including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer. They perform 8-bit oriented, bidirectional data transfers up to 100 kbit/s in the standard mode, or up to 400 kbit/s in the fast mode On-Chip Debug Support interface (OCDS)* trst tck tms tdi tdo I I I I O Low High High High High Debug logic reset input (IEEE1149.1 Test Logic Reset) Debug clock (IEEE1149.1 Test Clock) Test Mode Select (IEEE1149.1 Test Mode Select) Debug Data Input (IEEE1149.1 Test Data Input) Debug Data Output (IEEE1149.1 Test Data Output) Debug Data Output Enable Serial Peripheral Interface (SPI) Interface Provides full-duplex, synchronous communication between the core and other peripheral devices, including other MCUs. It can operate either as Master or Slave, with programmable clock rate, phase, and polarity. The maximum data rate is 1/4 of the system clock for a Slave, and 1/2 of the system clock for a Master. Write collision and overrun detection protect data, and Master mode fault detection for multi-master systems prevents bus conflict. Copyright (c) 2005 - 2008 Evatronix SA tdoenable O High R8051XC-DSN-1HV28F26S00-200 Page 6 of 8 R8051XC Configurable Microcontroller Configurable Microcontroller Verification Methods The core has been verified through extensive simulation and rigorous code coverage measurements. All subcomponents were functionally verified with an HDL testbench using their individual test suites. The CPU and ALU have been verified against a proprietary hardware modeler and behavioral models. The peripherals have also been verified in their own testbenches, based on either hardware or behavioral models. The core satisfies the requirements of the Reuse Methodology Manual and the VSIA Quality IP Metric. Quality IP Assessment IP Ease of Reuse Design & Verification Quality IP Maturity Vendor Assessment Total Score 97% 83% 100% 82% 89% Pin Description - Continued Name Type Polarity/ Bus size 4 4 45 45 45 45 High High High High Description Trace RAM signals (OCDS)* addr_buf0 addr_buf1 datao_buf0 datao_buf1 datai_buf0 datai_buf1 wr_buf0 wr_buf1 rd_buf0 rd_buf1 O O O O I I O O O O Trace buffer 0 address bus Trace buffer 1 address bus Trace buffer 0 data output Trace buffer 1 data output Trace buffer 0 data input Trace buffer 1 data input Trace buffer 0 write enable Trace buffer 1 write enable Trace buffer 0 read enable Trace buffer 1 read enable Hold interface The R8051XC has been verified through extensive functional simulation and it has achieved high Code Coverage simulation results. Code Coverage Statement Branch Condition Triggering Path Toggle Metric 100 % 96.7 % 80.5 % 62.9 % 93.1 % hold holda intoccur I O O High High High Hold mode request Hold mode acknowledge signal Interrupt occured in Hold mode I2CTM interface scli sclo sdai sdao I O I O High High I2C serial clock input I2C serial clock output I2C data input I2C data output Secondary I2CTM interface scl2i I O I O High High I2C serial clock input I2C serial clock output I2C data input I2C data output scl2o sda2i sda2o The trial ATPG coverage figures met the requirements and reached level of 99%. Additionally the value of IDDQ reached level of 99%. Related Products SPI-MS - Serial Peripheral Interface supporting slave as well as master capability with own rate generator and programmable polarity of serial clock. A dedicated set of slave selection signals facilitates integration in multi slave system; I2C - controller which meets the original Philips I2C bus interface controller specification requirements. It may operate in one of the following transmission modes: Master Transmitter, Master Receiver, Slave Transmitter and Slave Receiver with transmission rates up to 400 kHz; I2CS - controller compatible with the Philips I2C bus interface slave controller. It may operate in one of the following transmission modes: Slave Transmitter and Slave Receiver with transmission rates up to 400 kHz. SPI interface ssn misoi misoo misotri mosii mosio mositri scki I I O O I O O I O O O Low High High Rise/Fall Rise/Fall High 8 SPI Slave Select input SPI Master Input / Slave Output bidirectional port - input part SPI Master Input / Slave Output bidirectional port - output part SPI Master Input / Slave Output bidirectional port - output enable SPI Master Output / Slave Input bidirectional port - input part SPI Master Output / Slave Input bidirectional port - output part SPI Master Output / Slave Input bidirectional port - output enable SPI Serial Clock bidirectional port - input part SPI Serial Clock bidirectional port - output part SPI Serial Clock bidirectional port - output enable 8-bit output port to control external slave devices Third Party Reference The R8051XC core may be delivered with debug instrumentation implemented and ready to work with Keil uVision debug environment. For more details about On Chip Debug Support visit Evatronix web site http://www.evatronix.pl. Following is a link to the R8051XC on the list of devices that are supported by the Keil development tools http://www.keil.com/dd/chip/4122.htm. scko scktri spssn *The OCI and OCDS are mutually exclusive Copyright (c) 2005 - 2008 Evatronix SA R8051XC-DSN-1HV28F26S00-200 Page 7 of 8 R8051XC Configurable Microcontroller Configurable Microcontroller Example Application The following figure presents an example application of the R8051XC core. Standard Deliverables HDL source code for the R8051XC Synthesis support (Synopsys) Options Typically the core is delivered as either VHDL or Verilog source code for ASIC implementations. The following options may be ordered according to user's requirements. Pre-configured R8051XC-A or R8051XC-B versions Fully configurable R8051XC-F version EDIF netlist for FPGA and low volume production Complete debug solution including software plug-in for Keil environment and USB Pod Annual maintenance On-site support and training A complete set of synthesis scripts Simulation support (MTI, Cadence) A set of scripts and macros Extensive VHDL or Verilog 2001 Test Bench that instantiates: The R8051XC Microcontroller The R8051XC CPU behavioral model Clock and reset generator External RAM model Program Memory model including random code generation mode Memory access comparators Verification components that drive and compare pins dedicated to several peripherals of the R8051XC A collection of 8051 assembler programs which are executed directly by the Test Bench A set of expected results Documentation Design Specification Verification Specification Test Plan Integration Manual Application Notes Configuration tool for easy use with the R8051XC-F Reference design for propriety development board This design uses the R8051XC and illustrates how to build and connect memories and port modules Product Versions The core can be delivered as either pre-configured version (A or B) or fully configurable source code. R8051XC-A - predefined configuration with peripheral set compatible to Intel 80C31 including: 2 Timers, Serial port, 4 Parallel Ports, 2 Level Interrupt Controller R8051XC-B - predefined configuration with peripherals compatible to Siemens 80C515 and 80C517, including: 3 Timers, 2 Serial ports, 4 Parallel ports, Watchdog, Multiplication-Division Unit, Dual DPTR R8051XC-F - fully configurable version extending R8051XC-B with: I2C serial port, SPI port, memory banking, arithmetic support for DPTRs, 8 DPTRs, possibility of instruction set reduction. All trademarks mentioned in this document are trademarks of their respective owners Headquarters Przybyy 2, 43-300 Bielsko Biala, Poland, Phone: +48 33 499 59 00, Fax: +48 33 499 59 18 sekretariat@evatronix.pl, www.evatronix.pl Copyright (c) 2005 - 2008 Evatronix SA R8051XC-DSN-1HV28F26S00-200 Page 8 of 8 |
Price & Availability of R8051XC
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |